1. Field of the Invention
The present invention relates to a digital synchronization circuit for generating an output clock signal which is in synchronization with a phase of an input data signal.
2. Description of the Background Art
A method of implementing a synchronization circuit for generating an output clock signal which is in synchronization with a phase of an input data signal serially transmitted from an external portion of a chip is disclosed in IEEE JOURNAL OF SOLID-STATE CIRCUITS, Vol. 25, No. 6,DECEMBER 1990, pp. 1385-1394, B. Kim, D. N. Helman and P. Gray, xe2x80x9cA 30-MHz Hybrid Analog/Digital Clock Recovery Circuit in 2-xcexcm CMOS.xe2x80x9d
Disclosed in the reference is a method of generating a desired clock signal by using a polyphase clock signal generated by a voltage controlled oscillator (hereinafter abbreviated as a VCO) including inverter columns connected in a ring like form and whose delay times are controllable.
A polyphase clock generation circuit generating the polyphase clock signal has a PLL (phase locked loop) structure which is controlled such that an oscillation frequency of the VCO is the same as an operation frequency of the input data signal which is input from the external portion of the chip. The signals are separately transmitted from nodes of inverter columns connected in the ring like form in the VCO, so that a plurality of clock signals having different phases but the same phase difference, i.e., polyphase clock signals, are output.
Referring to FIG. 14, a conventional digital synchronization circuit 9000 using polyphase clock signals will be described.
Conventional digital synchronization circuit 9000 includes: a polyphase clock generation circuit 910 outputting clock signals CLK1-CLKn to n signal lines; n-bit latch circuits 920 and 930; a clock phase determination circuit 950; and a selector 960 selecting and outputting one of n clock signals CLK1 to CLKn.
Latch circuit 920 includes n D type flip-flops FF1 to FFn. Flip-flops FFi (i=1 to n) is arranged in correspondence with clock signal CLKi.
Next, an arrangement of conventional digital synchronization circuit 9000 will be described. Clock signals CLK1 to CLKn are respectively connected to clock input terminals of flip-flops FF1 to FFn and the first to nth data input terminals of selector 960. Input data signals DIN are applied to all of data input terminals D of flip-flops FF1 to FFn.
Further, output signals from flip-flops FF1 to FFn are respectively applied to the first to the nth bit data input terminals of latch circuit 30. Clock signal CLKn is applied to the clock input terminal of latch circuit 930.
The n-bit output signal output from latch circuit 930 is applied to the input terminal of clock phase determination circuit 950.
A clock selection signal CSL from clock phase determination circuit 950 is applied to a control input terminal of selector 960, and an output clock signal OUTCLK is output from an output terminal of selector 960.
Now, an operation of conventional digital synchronization circuit 9000 will be described.
Clock signals CLK1 to CLKn having different phases and having the same frequency as that of input data signal DIN are output from polyphase clock generation circuit 910. Input data signals DIN are respective latched at flip-flops FF1 to FFn by clock signals CLK1 to CLKn. More specifically, input data signals DIN are sampled by clock signals CLK1 to CLKn, and the sampled data are retained in flip-flops FF1 to FFn.
The sampled data in FF1 to FFn are received by latch circuit 930 in the next stage by clock signal CLKn.
The n-bit data in latch circuit 930 is applied to clock phase determination circuit 950.
Here, clock phase determination circuit 950 determines the change in potential level of the signal which has been obtained by sampling input data signal DIN in time series, so that a clock selection signal CSL for selecting one of clock signals CLK1 to CLKn is output as a suitable clock signal for correctly sampling input data signal DIN.
Selector 960 selects one of clock signals CLK1 to CLKn in accordance with a value of dock selection signal CSL. The selected signal is output as output clock signal OUTCLK.
As described above, digital synchronization circuit 9000 selects one of clock signals CLK1 to CLKn having a phase in synchronization with input data signal DIN for outputting the selected signal as output clock signal OUTCLK. Thus, the synchronization circuit by digital control is achieved.
In the case of a digital synchronization circuit selecting one of clock signals CLK1 to CLKn by selector 960 for outputting the selected signal as output clock signal OUTCLK in synchronization with input data signal DIN, a hazard, which is an undesirable change in potential level of a signal in a short period of time, may be caused to output clock signal OUTCLK in switching clock signals at a certain transition timing of clock selection signal CSL.
The hazard caused to output clock signal OUTCLK will be described with reference to FIG. 15.
Assume that, at a time t100, the clock signal selected by selector 960 in accordance with the value of clock selection signal CSL switches from clock signal CLKc to CLKc+1. Further, assume that potentials of clock signals CLKc and CLKc+1 are both at an xe2x80x9cHxe2x80x9d level. Here, c=1, 1 less than c  less than nxe2x88x922 (c: integer) or c=nxe2x88x922.
At the time, potentials of clock signals CLKc and CLKc+1 are both at the xe2x80x9cHxe2x80x9d level, so that even if the signal selected by selector 960 is switched, no hazard is caused to output clock signal OUTCLK.
Next, at a time t101, assume that the clock signal selected by selector 960 in accordance with the value of clock selection signal CSL switches from clock signal CLKc+1 to CLKc+2. Further, assume that the potential level of clock signal CLKc+1 changes from an xe2x80x9cLxe2x80x9d level to the xe2x80x9cHxe2x80x9d level shortly before time t101, and the potential level of clock signal CLKc+2 changes from the xe2x80x9cLxe2x80x9d to xe2x80x9cHxe2x80x9d level shortly after time t101.
Then, the potential level of output clock signal OUTCLK from selector 960 changes from the xe2x80x9cLxe2x80x9d to xe2x80x9cHxe2x80x9d level shortly before time t101, then to the xe2x80x9cLxe2x80x9d level at t101, and further to xe2x80x9cHxe2x80x9d level shortly after the t101.
More specifically, a hazard is caused to the potential of output clock signal OUTCLK, that is characterized by undesirable changes in potential level in a short period of time.
The hazard caused to output clock signal OUTCLK would adversely affect the operation of the external circuit receiving output clock signal OUTCLK.
Therefore, an object of the present invention is to provide a digital synchronization circuit capable of outputting an output clock signal which is stably in synchronization with an input data signal without causing a hazard.
The digital synchronization circuit according to one aspect of the present invention includes: a clock generation circuit generating a plurality of clock signals having substantially the same frequency and having different phases; a selection circuit selectively outputting corresponding one having plurality of clock signals in accordance with a first selection signal; a clock determination circuit sampling the input data signal using the plurality of clock signals and selecting one of the plurality of clock signals based on the sampling result for outputting a second selection signal indicating the selection result; and a selection control circuit adjusting a timing at which the second selection circuit changes and outputting the first selection signal. The selection control circuit changes a value of the first selection signal from a first value to a second value in a period in which potentials of clock signals represented by the first and second values match in response to the change in value of the second selection signal from the first value to the second value.
Preferably, the selection control circuit includes: a clock selection circuit selectively outputting a clock signal represented by the value of the second selection signal of the plurality of clock signals; and a latch circuit latching the second selection signal and outputting the first selection signal in accordance with an output from the clock selection circuit.
Preferably, the selection control circuit includes a clock selection circuit having a plurality of first data input terminals respectively arranged in correspondence with the plurality of clock signals and supplied with respective clock signals, a first control input terminal supplied with the second selection signal, and a first output terminal. The clock selection circuit selects of the plurality of first data input terminals in accordance with the second selection signal for outputting the clock signal applied to the selected first data input terminal from the first output terminal. The selection control circuit further includes a latch circuit having a clock input terminal receiving the clock signal output from the first output terminal, a second data input terminal supplied with the second selection signal and a second output terminal. The latch circuit latches the second selection signal in accordance with an input to the clock input terminal for outputting the first selection signal from the second output terminal. The selection circuit includes a plurality of third data input terminals respectively arranged in correspondence with the plurality of clock signals and supplied with corresponding clock signals, a second control input terminal supplied with the second selection signal, and a third output terminal. The selection circuit selects one of the plurality of third data input terminals in accordance with the first selection signal for outputting the clock signal supplied to the selected third data input terminal from the third output terminal.
Particularly, the digital synchronization circuit further includes a plurality of signal lines transmitting the plurality of clock signals which are connected to the plurality of the first and third data input terminals such that the clock signals respectively represented by values of the second and first selection signals and input to the first and third data input terminals are the same when the values of the second and first selection signals are the same. Alternatively, the plurality of signal lines are connected to the plurality of first and third data input terminals such that there is a prescribed phase difference in the clock signals respectively represented by the values of the second and first selection signals and input to the first and third data input terminals when the values of the second and first selection signals are the same.
Preferably, the clock determination circuit selects one of the plurality of clock signals that changes in a prescribed relationship with respect to a transition timing of the input data signal, and outputs the second selection signal representing the selected clock signal. Particularly, the clock determination circuit selects one of the plurality of clock signals that rises or falls at the timing which is the closest to a prescribed timing of the input data signal in an input period.
According to the digital synchronization circuit, the value of the first selection signal can be changed at a timing different from that at which the value of the second selection signal is changed.
Accordingly, a transition in the first selection signal is achieved when potentials of two clock signals to be switched are the same, so that a clock signal without any hazard is obtained as an output from the selection circuit.
A digital synchronization circuit according to another aspect of the present invention includes: a clock generation circuit generating a plurality of clock signals having substantially the same frequency and having different phases; a clock determination circuit sampling an input data signal using the plurality of clock signals and selecting one of the plurality of clock signals based on the sampling result for outputting a selection signal indicating the selection result; a selection circuit selecting and outputting one of the plurality of clock signals having a prescribed phase difference with respect to the clock signal represented by the value of the selection signal; and a logic circuit eliminating and outputting a high frequency component from an output from the selection circuit.
Preferably, a prescribed amount of time is required after input of the signal to the selection circuit and before output of the corresponding signal from the logic circuit. The selection circuit selects a clock signal with a phase which is advanced with respect to that of the clock signal represented by the value of the selection signal by a prescribed amount of time.
Particularly, the selection circuit includes a plurality of data input terminals respectively arranged in correspondence with the plurality of clock signals and supplied with corresponding clock signals, a control input terminal supplied with the selection signal, and an output terminal. The selection circuit selects one of the plurality of data input terminals that is supplied with the clock signal having a prescribed phase difference with respect to the dock signal represented by the value of the selection signal for outputting the clock signal applied to the selected data input terminal from the output terminal.
Alternatively, the selection circuit may include a calculation circuit shifting the value of the selection signal by an amount corresponding to the prescribed phase difference and a circuit including a plurality of data input terminals respectively arranged in correspondence with the plurality of clock signals and supplied with corresponding clock signals; a control input terminal supplied with an output from the calculation circuit and output terminal. The circuit selects one of the plurality of data input terminals that is supplied with a clock signal represented by the value of the output from the calculation circuit for outputting the clock signal applied to the selected data input terminal from the output terminal.
Preferably, the clock determination circuit selects one of the plurality of clock signals that changes in a prescribed relationship with respect to a transition timing of the input data signal for outputting the selection signal representing the selected clock signal. Particularly, the clock determination circuit selects one of the plurality of clock signals that rises or falls at a timing which is the closest to a prescribed timing of the input data signal in an input period.
Preferably, the logic circuit includes a filter circuit for eliminating a high frequency component, and a waveform adjusting circuit for adjusting an output waveform from the filter circuit. The waveform adjusting circuit includes a logic gate circuit.
According to the above mentioned digital synchronization circuit, the clock signal having a phase advanced by a propagation delay time caused by the selection circuit and the logic circuit is selected, and the signal obtained by eliminating the high frequency component from the selected clock signal is output. Thus, an adverse affect of the propagation delay time caused by the selection circuit and the logic circuit is eliminated and the clock signal without any hazard can effectively be obtained.
Further, the filter circuit for eliminating the high frequency component from the selection output signal and the waveform adjusting circuit for adjusting undesired variations in the output signal waveform from the filter circuit are provided, whereby a signal without being adversely affected by a hazard is effectively and readily be obtained even if a hazard is caused to the output signal from the selection circuit.
Furthermore, the waveform adjusting circuit is in the form of the logic gate circuit, so that a circuit scale can effectively be reduced.